module ysyx_050369_pc_reg(
    input               clk,
    input               rst,
    input  [31:0]       nxpc,
    input               ex_fence_flag,
    input               pc_stop,
    input               jump_valid   ,
    input               pre_jump,
    input  [31:0]       pre_pc,
    output reg [31:0]   pc

);
    always@(posedge clk) begin
        if(rst)begin
    `ifdef ysyx_050369_SOC
            pc <= 32'h30000000;
    `else
            pc <= 32'h80000000;
    `endif
        end
        else if (pc_stop) begin
            pc <= pc;
        end
        else if(jump_valid || ex_fence_flag)  begin
            pc <= nxpc;
        end
        else if (pre_jump)begin
            pc <= pre_pc;
        end
        else begin
            pc <= pc+4;
        end
    end

endmodule